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1. general description nxp semiconductors designed the lpc2458 microcontroller around a 16-bit/32-bit arm7tdmi-s cpu core with real-time debug interfaces that include both jtag and embedded trace. the lpc2458 has 512 kb of on-chip high-speed ?ash memory. this ?ash memory includes a special 128-bit wide memory interface and accelerator architecture that enables the cpu to execute sequential instructions from ?ash memory at the maximum 72 mhz system clock rate. this feature is available only on the lpc2000 arm microcontroller family of products. the lpc2458 can execute both 32-bit arm and 16-bit thumb instructions. support for the two instruction sets means engineers can choose to optimize their application for either performance or code size at the sub-routine level. when the core executes instructions in thumb state it can reduce code size by more than 30 % with only a small loss in performance while executing instructions in arm state maximizes core performance. the lpc2458 microcontroller is ideal for multi-purpose communication applications. it incorporates a 10/100 ethernet media access controller (mac), a usb full-speed device/host/otg controller with 4 kb of endpoint ram, four uarts, two controller area network (can) channels, an spi interface, two synchronous serial ports (ssp), three i 2 c interfaces, and an i 2 s interface. supporting this collection of serial communications interfaces are the following feature components; an on-chip 4 mhz internal precision oscillator, 98 kb of total ram consisting of 64 kb of local sram, 16 kb sram for ethernet, 16 kb sram for general purpose dma, 2 kb of battery powered sram, and an external memory controller (emc). these features make this device optimally suited for communication gateways and protocol converters. complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit adc, 10-bit dac, two pwm units, four external interrupt pins, and up to 136 fast gpio lines. the lpc2458 connects 64 of the gpio pins to the hardware based vector interrupt controller (vic) that means these external inputs can generate edge-triggered interrupts. all of these features make the lpc2458 particularly suitable for industrial control and medical systems. 2. features n arm7tdmi-s processor, running at up to 72 mhz. n 512 kb on-chip ?ash program memory with in-system programming (isp) and in-application programming (iap) capabilities. flash program memory is on the arm local bus for high performance cpu access. n 98 kb on-chip sram includes: u 64 kb of sram on the arm local bus for high performance cpu access. u 16 kb sram for ethernet interface. can also be used as general purpose sram. lpc2458 single-chip 16-bit/32-bit micro; 512 kb ?ash, ethernet, can, isp/iap, usb 2.0 device/host/otg, external memory interface rev. 02 25 november 2008 product data sheet
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 2 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller u 16 kb sram for general purpose dma use also accessible by the usb. u 2 kb sram data storage powered from the real-time clock (rtc) power domain. n dual advanced high-performance bus (ahb) system allows simultaneous ethernet dma, usb dma, and program execution from on-chip ?ash with no contention. n emc provides support for asynchronous static memory devices such as ram, rom and ?ash, as well as dynamic memories such as single data rate sdram. n advanced vectored interrupt controller (vic), supporting up to 32 vectored interrupts. n general purpose dma controller (gpdma) on ahb that can be used with the ssp, i 2 s, and sd/mm interface as well as for memory-to-memory transfers. n serial interfaces: u ethernet mac with mii/rmii interface and associated dma controller. these functions reside on an independent ahb. u usb 2.0 full-speed dual port device/host/otg controller with on-chip phy and associated dma controller. u four uarts with fractional baud rate generation, one with modem control i/o, one with irda support, all with fifo. u can controller with two channels. u spi controller. u two ssp controllers, with fifo and multi-protocol capabilities. one is an alternate for the spi port, sharing its interrupt. ssps can be used with the gpdma controller. u three i 2 c-bus interfaces (one with open-drain and two with standard port pins). u i 2 s (inter-ic sound) interface for digital audio input or output. it can be used with the gpdma. n other peripherals: u sd/mmc memory card interface. u 136 general purpose i/o pins with con?gurable pull-up/down resistors. u 10-bit adc with input multiplexing among 8 pins. u 10-bit dac. u four general purpose timers/counters with 8 capture inputs and 10 compare outputs. each timer block has an external count input. u two pwm/timer blocks with support for three-phase motor control. each pwm has an external count inputs. u rtc with separate power domain, clock source can be the rtc oscillator or the apb clock. u 2 kb sram powered from the rtc power pin, allowing data to be stored when the rest of the chip is powered off. u watchdog timer (wdt). the wdt can be clocked from the internal rc oscillator, the rtc oscillator, or the apb clock. n standard arm test/debug interface for compatibility with existing tools. n emulation trace module supports real-time trace. n single 3.3 v power supply (3.0 v to 3.6 v). n three reduced power modes: idle, sleep, and power-down. n four external interrupt inputs con?gurable as edge/level sensitive. all pins on port 0 and port 2 can be used as edge sensitive interrupt sources.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 3 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller n processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, ethernet wake-up interrupt, can bus activity, port 0/2 pin interrupt). n two independent power domains allow ?ne tuning of power consumption based on needed features. n each peripheral has its own clock divider for further power saving. these dividers help reducing active power by 20 % to 30 %. n brownout detect with separate thresholds for interrupt and forced reset. n on-chip power-on reset. n on-chip crystal oscillator with an operating range of 1 mhz to 25 mhz. n 4 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. when used as the cpu clock, does not allow can and usb to run. n on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high frequency crystal. may be run from the main oscillator, the internal rc oscillator, or the rtc oscillator. n boundary scan for simpli?ed board testing. n versatile pin function selections allow more possibilities for using on-chip peripheral functions. 3. applications n industrial control n medical systems n protocol converter n communications 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc2458fet180 tfbga180 thin ?ne-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 table 2. ordering options type number flash (kb) sram (kb) external bus ethernet usb otg/ ohc/ dev +4kb fifo can channels sd/ mmc gp dma adc channels dac channels temp range local bus ethernet buffer gp/usb rtc total lpc2458fet180 512 64 16 16 2 98 16-bit mii/ rmii yes 2 yes yes 8 1 - 40 c to +85 c
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 4 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 5. block diagram fig 1. lpc2458 block diagram power domain 2 lpc2458 a[19:0] d[15:0] external memory controller alarm 002aad093 pwm0, pwm1 arm7tdmi-s pll eint3 to eint0 flash p3, p4 p0, p1, p2, legacy gpi/o 64 pins total p0, p1 sck, sck0 mosi, mosi0 ssel, ssel0 sck1 mosi1 miso1 ssel1 scl0, scl1, scl2 i2srx_clk i2stx_clk i2srx_ws i2stx_ws 8 ad0 rtcx1 rtcx2 mciclk, mcipwr rxd0, rxd2, rxd3 txd1 rxd1 rd1, rd2 td1, td2 can1, can2 port 1 xtal1 tck tdo extin0 xtal2 reset trst tdi tms high-speed gpio 136 pins total port 2 64 kb sram 512 kb flash internal controllers test/debug interface emulation trace module trace signals ahb bridge ahb bridge ethernet mac with dma 16 kb sram master port ahb to ahb bridge slave port system clock system functions internal rc oscillator v dda v dd(3v3) v dd(dcdc)(3v3) vref v ssa , v ssio, v sscore vic 16 kb sram usb device/ host/otg with 4 kb ram and dma gpdma controller i 2 s interface spi, ssp0 interface i2srx_sda i2stx_sda miso, miso0 ssp1 interface sd/mmc card interface mcicmd, mcidat[3:0] txd0, txd2, txd3 uart0, uart2, uart3 uart1 dtr1, rts1 dsr1, cts1, dcd1, ri1 i 2 c0, i 2 c1, i 2 c2 sda0, sda1, sda2 external interrupts capture/compare timer0/timer1/ timer2/timer3 a/d converter d/a converter 2 kb battery ram rtc oscillator real- time clock watchdog timer system control 2 cap0/cap1/ cap2/cap3 4 mat2, 2 mat3, 2 mat1/mat0 6 pwm0, pwm1 1 pcap0, 2 pcap1 aout vbat ahb to apb bridge sram mii/rmii v bus dbgen p0, p2 ahb2 ahb1 control lines
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 5 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 6. pinning information 6.1 pinning fig 2. lpc2458 pinning tfbga180 package 002aad094 lpc2458 246810121314 1357911 ball a1 index area p n m l k j g e h f d c b a transparent top view table 3. pin allocation table pin symbol pin symbol pin symbol pin symbol row a 1 p3[12]/d12 2 p3[2]/d2 3 p0[3]/rxd0 4 p3[9]/d9 5 p1[1]/enet_txd1 6 p3[8]/d8 7 p1[10]/enet_rxd1 8 p1[15]/ enet_ref_clk/ enet_rx_clk 9 p1[3]/enet_txd3/ mcicmd/pwm0[2] 10 v sscore 11 p0[4]/i2srx_clk/rd2/ cap2[0] 12 p1[11]/enet_rxd2/ mcidat2/pwm0[6] 13 p0[9]/i2stx_sda/ mosi1/mat2[3] 14 p1[12]/enet_rxd3/ mcidat3/pcap0[0] 15 - 16 - row b 1 tdo 2 p3[11]/d11 3 p3[10]/d10 4 v ssio 5 p1[0]/enet_txd0 6 p1[8]/enet_crs_dv/e net_crs 7 p1[2]/enet_txd2/ mciclk/pwm0[1] 8 p1[16]/enet_mdc 9 p4[29]/ mat2[1]/rxd3 10 p1[6]/enet_tx_clk/ mcidat0/pwm0[4] 11 p0[5]/i2srx_ws/td2/ cap2[1] 12 p0[7]/i2stx_clk/sck1 /mat2[1] 13 p1[5]/enet_tx_er/ mcipwr/pwm0[3] 14 p4[13]/a13 15 - 16 - row c 1 p3[13]/d13 2 tms 3 tdi 4 rtck 5v dd(3v3) 6 p1[4]/enet_tx_en 7 p4[30]/ cs0 8 p4[24]/ oe 9 p1[17]/enet_mdio 10 p4[15]/a15 11 v ssio 12 p0[8]/i2stx_ws/ miso1/mat2[2]
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 6 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 13 p1[7]/enet_col/ mcidat1/pwm0[5] 14 p2[1]/pwm1[2]/rxd1/ pipestat0 15 - 16 - row d 1 p0[26]/ad0[3]/ aout/rxd3 2 tck 3 p3[4]/d4 4 trst 5 p0[2]/txd0 6 p3[0]/d0 7 p1[9]/enet_rxd0 8 p1[14]/enet_rx_er 9 p4[25]/ we 10 p4[28]/ mat2[0]/txd3 11 p0[6]/i2srx_sda/ ssel1/mat2[0] 12 p2[0]/pwm1[1]/txd1/ traceclk 13 v ssio 14 p1[13]/enet_rx_dv 15 - 16 - row e 1 p0[24]/ad0[1]/ i2srx_ws/cap3[1] 2v dd(3v3) 3 p3[5]/d5 4 p0[25]/ad0[2]/ i2srx_sda/txd3 5 dbgen 6 p3[1]/d1 7 p4[31]/ cs1 8 p4[14]/a14 9v dd(dcdc)(3v3) 10 v dd(3v3) 11 p2[2]/pwm1[3]/ cts1/pipestat1 12 v dd(3v3) 13 p2[3]/pwm1[4]/ dcd1/pipestat2 14 p2[4]/pwm1[5]/ dsr1/tracesync 15 - 16 - row f 1 p3[14]/d14 2 v dda 3v ssa 4 p3[6]/d6 5 p0[23]/ad0[0]/ i2srx_clk/cap3[0] 678 9 10 p4[12]/a12 11 p4[11]/a11 12 p2[5]/pwm1[6]/ dtr1/tracepkt0 13 p2[6]/pcap1[0]/ ri1/tracepkt1 14 p4[27]/ bls1 15 - 16 - row g 1v dd(dcdc)(3v3) 2 vref 3 p3[7]/d7 4 p3[15]/d15 5 p3[3]/d3 6 7 8 9 10 n.c. 11 p2[7]/rd2/ rts1/tracepkt2 12 p4[10]/a10 13 v ssio 14 p2[8]/td2/ txd2/tracepkt3 15 - 16 - row h 1 n.c. 2 rst out 3 v sscore 4v ssio 5 alarm 6 7 8 9 10 p4[5]/a5 11 p2[9]/ usb_connect1/ rxd2/extin0 12 p4[9]/a9 13 p0[15]/txd1/ sck0/sck 14 p0[16]/rxd1/ ssel0/ssel 15 - 16 - row j 1 reset 2 rtcx1 3 rtcx2 4 p0[12]/ usb_ppwr2/ miso1/ad0[6] 5 p0[13]/usb_up_led2/ mosi1/ad0[7] 678 table 3. pin allocation table continued pin symbol pin symbol pin symbol pin symbol
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 7 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 9 10 p0[19]/dsr1/ mciclk/sda1 11 p4[8]/a8 12 p0[17]/cts1/ miso0/miso 13 p0[18]/dcd1/ mosi0/mosi 14 v dd(3v3) 15 - 16 - row k 1 vbat 2 p1[31]/ usb_o vrcr2/ sck1/ad0[5] 3 p1[30]/usb_pwrd2/ v bus /ad0[4] 4 xtal2 5 p0[29]/usb_d+1 6 p1[20]/usb_tx_dp1/ pwm1[2]/sck0 7 p3[26]/mat0[1]/ pwm1[3] 8v dd(3v3) 9 p4[3]/a3 10 p4[6]/a6 11 p0[21]/ri1/ mcipwr/rd1 12 p4[7]/a7 13 p4[26]/ bls0 14 p0[20]/dtr1/ mcicmd/scl1 15 - 16 - row l 1 p2[29]/dqmout1 2 xtal1 3 p0[27]/sda0 4 v dd(3v3) 5 p1[18]/usb_up_led1/ pwm1[1]/cap1[0] 6 p4[0]/a0 7 p1[25]/ usb_ls1/ usb_hsten1/mat1[1] 8v sscore 9v ssio 10 p0[10]/txd2/sda2/ mat3[0] 11 v dd(3v3) 12 n.c. 13 v ssio 14 p0[22]/rts1/ mcidat0/td1 15 - 16 - row m 1 p0[28]/scl0 2 p2[28]/dqmout0 3 p3[25]/mat0[0]/ pwm1[2] 4 p3[23]/cap0[0]/ pcap1[0] 5 p0[14]/ usb_hsten2/ usb_connect2/ ssel1 6 p1[22]/usb_rcv1/ usb_pwrd1/mat1[0] 7 p4[1]/a1 8 p4[2]/a2 9 p1[27]/ usb_int1/ usb_o vrcr1/cap0[1] 10 p0[0]/rd1/txd3/sda1 11 p2[13]/ eint3/ mcidat3/i2stx_sda 12 p2[11]/ eint1/ mcidat1/i2stx_clk 13 p2[10]/ eint0 14 p4[19]/a19 15 - 16 - row n 1 p0[31]/usb_d+2 2 usb_d - 2 3 p3[24]/cap0[1]/ pwm1[1] 4 p0[30]/usb_d - 1 5 p2[19]/clkout1 6 p1[21]/usb_tx_dm1/ pwm1[3]/ssel0 7 p1[23]/usb_rx_dp1/ pwm1[4]/miso0 8 p2[21]/ d ycs1 9v dd(dcdc)(3v3) 10 p1[29]/usb_sda1/ pcap1[1]/mat0[1] 11 p0[1]/td1/rxd3/scl1 12 p4[16]/a16 13 p4[17]/a17 14 p2[12]/ eint2/ mcidat2/i2stx_ws 15 - 16 - row p 1 p2[24]/ckeout0 2 p2[25]/ckeout1 3 p2[18]/clkout0 4 v ssio 5 p1[19]/ usb_tx_e1/ usb_ppwr1/cap1[1] 6 p2[20]/ d ycs0 7 p1[24]/usb_rx_dm1/ pwm1[5]/mosi0 8 p1[26]/ usb_sspnd1/ pwm1[6]/cap0[0] 9 p2[16]/ cas 10 p1[28]/usb_scl1/ pcap1[0]/mat0[0] 11 p2[17]/ ras 12 p0[11]/rxd2/scl2/ mat3[1] 13 p4[4]/a4 14 p4[18]/a18 15 - 16 - table 3. pin allocation table continued pin symbol pin symbol pin symbol pin symbol
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 8 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 6.2 pin description table 4. pin description symbol ball type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. p0[0]/rd1/ txd3/sda1 m10 [1] i/o p0[0] general purpose digital input/output pin. i rd1 can1 receiver input. o txd3 transmitter output for uart3. i/o sda1 i 2 c1 data input/output (this is not an open-drain pin). p0[1]/td1/rxd3/ scl1 n11 [1] i/o p0[1] general purpose digital input/output pin. o td1 can1 transmitter output. i rxd3 receiver input for uart3. i/o scl1 i 2 c1 clock input/output (this is not an open-drain pin). p0[2]/txd0 d5 [1] i/o p0[2] general purpose digital input/output pin. o txd0 transmitter output for uart0. p0[3]/rxd0 a3 [1] i/o p0[3] general purpose digital input/output pin. i rxd0 receiver input for uart0. p0[4]/ i2srx_clk/ rd2/cap2[0] a11 [1] i/o p0[4] general purpose digital input/output pin. i/o i2srx_clk receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . i rd2 can2 receiver input. i cap2[0] capture input for timer 2, channel 0. p0[5]/ i2srx_ws/ td2/cap2[1] b11 [1] i/o p0[5] general purpose digital input/output pin. i/o i2srx_ws receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . o td2 can2 transmitter output. i cap2[1] capture input for timer 2, channel 1. p0[6]/ i2srx_sda/ ssel1/mat2[0] d11 [1] i/o p0[6] general purpose digital input/output pin. i/o i2srx_sda receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . i/o ssel1 slave select for ssp1. o mat2[0] match output for timer 2, channel 0. p0[7]/ i2stx_clk/ sck1/mat2[1] b12 [1] i/o p0[7] general purpose digital input/output pin. i/o i2stx_clk transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . i/o sck1 serial clock for ssp1. o mat2[1] match output for timer 2, channel 1. p0[8]/ i2stx_ws/ miso1/mat2[2] c12 [1] i/o p0[8] general purpose digital input/output pin. i/o i2stx_ws transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . i/o miso1 master in slave out for ssp1. o mat2[2] match output for timer 2, channel 2.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 9 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p0[9]/ i2stx_sda/ mosi1/mat2[3] a13 [1] i/o p0[9] general purpose digital input/output pin. i/o i2stx_sda transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . i/o mosi1 master out slave in for ssp1. o mat2[3] match output for timer 2, channel 3. p0[10]/txd2/ sda2/mat3[0] l10 [1] i/o p0[10] general purpose digital input/output pin. o txd2 transmitter output for uart2. i/o sda2 i 2 c2 data input/output (this is not an open-drain pin). o mat3[0] match output for timer 3, channel 0. p0[11]/rxd2/ scl2/mat3[1] p12 [1] i/o p0[11] general purpose digital input/output pin. i rxd2 receiver input for uart2. i/o scl2 i 2 c2 clock input/output (this is not an open-drain pin). o mat3[1] match output for timer 3, channel 1. p0[12]/ usb_ppwr2/ miso1/ad0[6] j4 [2] i/o p0[12] general purpose digital input/output pin. o usb_ppwr2 port power enable signal for usb port 2. i/o miso1 master in slave out for ssp1. i ad0[6] a/d converter 0, input 6. p0[13]/ usb_up_led2/ mosi1/ad0[7] j5 [2] i/o p0[13] general purpose digital input/output pin. o usb_up_led2 usb port 2 goodlink led indicator. it is low when device is con?gured (non-control endpoints enabled). it is high when the device is not con?gured or during global suspend. i/o mosi1 master out slave in for ssp1. i ad0[7] a/d converter 0, input 7. p0[14]/ usb_hsten2/ usb_connect2/ ssel1 m5 [1] i/o p0[14] general purpose digital input/output pin. o usb_hsten2 host enabled status for usb port 2. o usb_connect2 softconnect control for usb port 2. signal used to switch an external 1.5 k w resistor under software control. used with the softconnect usb feature. i/o ssel1 slave select for ssp1. p0[15]/txd1/ sck0/sck h13 [1] i/o p0[15] general purpose digital input/output pin. o txd1 transmitter output for uart1. i/o sck0 serial clock for ssp0. i/o sck serial clock for spi. p0[16]/rxd1/ ssel0/ssel h14 [1] i/o p0[16] general purpose digital input/output pin. i rxd1 receiver input for uart1. i/o ssel0 slave select for ssp0. i/o ssel slave select for spi. p0[17]/cts1/ miso0/miso j12 [1] i/o p0[17] general purpose digital input/output pin. i cts1 clear to send input for uart1. i/o miso0 master in slave out for ssp0. i/o miso master in slave out for spi. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 10 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p0[18]/dcd1/ mosi0/mosi j13 [1] i/o p0[18] general purpose digital input/output pin. i dcd1 data carrier detect input for uart1. i/o mosi0 master out slave in for ssp0. i/o mosi master out slave in for spi. p0[19]/dsr1/ mciclk/sda1 j10 [1] i/o p0[19] general purpose digital input/output pin. i dsr1 data set ready input for uart1. o mciclk clock output line for sd/mmc interface. i/o sda1 i 2 c1 data input/output (this is not an open-drain pin). p0[20]/dtr1/ mcicmd/scl1 k14 [1] i/o p0[20] general purpose digital input/output pin. o dtr1 data terminal ready output for uart1. i/o mcicmd command line for sd/mmc interface. i/o scl1 i 2 c1 clock input/output (this is not an open-drain pin). p0[21]/ri1/ mcipwr/rd1 k11 [1] i/o p0[21] general purpose digital input/output pin. i ri1 ring indicator input for uart1. o mcipwr power supply enable for external sd/mmc power supply. i rd1 can1 receiver input. p0[22]/rts1/ mcidat0/td1 l14 [1] i/o p0[22] general purpose digital input/output pin. o rts1 request to send output for uart1. i/o mcidat0 data line 0 for sd/mmc interface. o td1 can1 transmitter output. p0[23]/ad0[0]/ i2srx_clk/ cap3[0] f5 [2] i/o p0[23] general purpose digital input/output pin. i ad0[0] a/d converter 0, input 0. i/o i2srx_clk receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . i cap3[0] capture input for timer 3, channel 0. p0[24]/ad0[1]/ i2srx_ws/ cap3[1] e1 [2] i/o p0[24] general purpose digital input/output pin. i ad0[1] a/d converter 0, input 1. i/o i2srx_ws receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . i cap3[1] capture input for timer 3, channel 1. p0[25]/ad0[2]/ i2srx_sda/ txd3 e4 [2] i/o p0[25] general purpose digital input/output pin. i ad0[2] a/d converter 0, input 2. i/o i2srx_sda receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . o txd3 transmitter output for uart3. p0[26]/ad0[3]/ aout/rxd3 d1 [2] [3] i/o p0[26] general purpose digital input/output pin. i ad0[3] a/d converter 0, input 3. o aout d/a converter output. i rxd3 receiver input for uart3. p0[27]/sda0 l3 [4] i/o p0[27] general purpose digital input/output pin. output is open-drain. i/o sda0 i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 11 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p0[28]/scl0 m1 [4] i/o p0[28] general purpose digital input/output pin. output is open-drain. i/o scl0 i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). p0[29]/usb_d+1 k5 [5] i/o p0[29] general purpose digital input/output pin. i/o usb_d+1 usb port 1 bidirectional d+ line. p0[30]/usb_d - 1n4 [5] i/o p0[30] general purpose digital input/output pin. i/o usb_d - 1 usb port 1 bidirectional d - line. p0[31]/usb_d+2 n1 [5] i/o p0[31] general purpose digital input/output pin. i/o usb_d+2 usb port 2 bidirectional d+ line. p1[0] to p1[31] i/o port 1: port 1 is a 32 bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. p1[0]/ enet_txd0 b5 [1] i/o p1[0] general purpose digital input/output pin. o enet_txd0 ethernet transmit data 0 (rmii/mii interface). p1[1]/ enet_txd1 a5 [1] i/o p1[1] general purpose digital input/output pin. o enet_txd1 ethernet transmit data 1 (rmii/mii interface). p1[2]/ enet_txd2/ mciclk/ pwm0[1] b7 [1] i/o p1[2] general purpose digital input/output pin. o enet_txd2 ethernet transmit data 2 (mii interface). o mciclk clock output line for sd/mmc interface. o pwm0[1] pulse width modulator 0, output 1. p1[3]/ enet_txd3/ mcicmd/ pwm0[2] a9 [1] i/o p1[3] general purpose digital input/output pin. o enet_txd3 ethernet transmit data 3 (mii interface). i/o mcicmd command line for sd/mmc interface. o pwm0[2] pulse width modulator 0, output 2. p1[4]/ enet_tx_en c6 [1] i/o p1[4] general purpose digital input/output pin. o enet_tx_en ethernet transmit data enable (rmii/mii interface). p1[5]/ enet_tx_er/ mcipwr/ pwm0[3] b13 [1] i/o p1[5] general purpose digital input/output pin. o enet_tx_er ethernet transmit error (mii interface). o mcipwr power supply enable for external sd/mmc power supply. o pwm0[3] pulse width modulator 0, output 3. p1[6]/ enet_tx_clk/ mcidat0/ pwm0[4] b10 [1] i/o p1[6] general purpose digital input/output pin. i enet_tx_clk ethernet transmit clock (mii interface). i/o mcidat0 data line 0 for sd/mmc interface. o pwm0[4] pulse width modulator 0, output 4. p1[7]/ enet_col/ mcidat1/ pwm0[5] c13 [1] i/o p1[7] general purpose digital input/output pin. i enet_col ethernet collision detect (mii interface). i/o mcidat1 data line 1 for sd/mmc interface. o pwm0[5] pulse width modulator 0, output 5. p1[8]/ enet_crs_dv/ enet_crs b6 [1] i/o p1[8] general purpose digital input/output pin. i enet_crs_dv/enet_crs ethernet carrier sense/data valid (rmii interface)/ ethernet carrier sense (mii interface). p1[9]/ enet_rxd0 d7 [1] i/o p1[9] general purpose digital input/output pin. i enet_rxd0 ethernet receive data 0 (rmii/mii interface). table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 12 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p1[10]/ enet_rxd1 a7 [1] i/o p1[10] general purpose digital input/output pin. i enet_rxd1 ethernet receive data 1 (rmii/mii interface). p1[11]/ enet_rxd2/ mcidat2/ pwm0[6] a12 [1] i/o p1[11] general purpose digital input/output pin. i enet_rxd2 ethernet receive data 2 (mii interface). i/o mcidat2 data line 2 for sd/mmc interface. o pwm0[6] pulse width modulator 0, output 6. p1[12]/ enet_rxd3/ mcidat3/ pcap0[0] a14 [1] i/o p1[12] general purpose digital input/output pin. i enet_rxd3 ethernet receive data (mii interface). i/o mcidat3 data line 3 for sd/mmc interface. i pcap0[0] capture input for pwm0, channel 0. p1[13]/ enet_rx_dv d14 [1] i/o p1[13] general purpose digital input/output pin. i enet_rx_dv ethernet receive data valid (mii interface). p1[14]/ enet_rx_er d8 [1] i/o p1[14] general purpose digital input/output pin. i enet_rx_er ethernet receive error (rmii/mii interface). p1[15]/ enet_ref_clk/ enet_rx_clk a8 [1] i/o p1[15] general purpose digital input/output pin. i enet_ref_clk/enet_rx_clk ethernet reference clock (rmii interface)/ ethernet receive clock (mii interface). p1[16]/ enet_mdc b8 [1] i/o p1[16] general purpose digital input/output pin. o enet_mdc ethernet miim clock. p1[17]/ enet_mdio c9 [1] i/o p1[17] general purpose digital input/output pin. i/o enet_mdio ethernet mi data input and output. p1[18]/ usb_up_led1/ pwm1[1]/ cap1[0] l5 [1] i/o p1[18] general purpose digital input/output pin. o usb_up_led1 usb port 1 goodlink led indicator. it is low when device is con?gured (non-control endpoints enabled). it is high when the device is not con?gured or during global suspend. o pwm1[1] pulse width modulator 1, channel 1 output. i cap1[0] capture input for timer 1, channel 0. p1[19]/ usb_tx_e1/ usb_ppwr1/ cap1[1] p5 [1] i/o p1[19] general purpose digital input/output pin. o usb_tx_e1 transmit enable signal for usb port 1 (otg transceiver). o usb_ppwr1 port power enable signal for usb port 1. i cap1[1] capture input for timer 1, channel 1. p1[20]/ usb_tx_dp1/ pwm1[2]/sck0 k6 [1] i/o p1[20] general purpose digital input/output pin. o usb_tx_dp1 d+ transmit data for usb port 1 (otg transceiver). o pwm1[2] pulse width modulator 1, channel 2 output. i/o sck0 serial clock for ssp0. p1[21]/ usb_tx_dm1/ pwm1[3]/ssel0 n6 [1] i/o p1[21] general purpose digital input/output pin. o usb_tx_dm1 d - transmit data for usb port 1 (otg transceiver). o pwm1[3] pulse width modulator 1, channel 3 output. i/o ssel0 slave select for ssp0. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 13 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p1[22]/ usb_rcv1/ usb_pwrd1/ mat1[0] m6 [1] i/o p1[22] general purpose digital input/output pin. i usb_rcv1 differential receive data for usb port 1 (otg transceiver). i usb_pwrd1 power status for usb port 1 (host power switch). o mat1[0] match output for timer 1, channel 0. p1[23]/ usb_rx_dp1/ pwm1[4]/miso0 n7 [1] i/o p1[23] general purpose digital input/output pin. i usb_rx_dp1 d+ receive data for usb port 1 (otg transceiver). o pwm1[4] pulse width modulator 1, channel 4 output. i/o miso0 master in slave out for ssp0. p1[24]/ usb_rx_dm1/ pwm1[5]/mosi0 p7 [1] i/o p1[24] general purpose digital input/output pin. i usb_rx_dm1 d - receive data for usb port 1 (otg transceiver). o pwm1[5] pulse width modulator 1, channel 5 output. i/o mosi0 master out slave in for ssp0. p1[25]/ usb_ls1/ usb_hsten1/ mat1[1] l7 [1] i/o p1[25] general purpose digital input/output pin. o usb_ls1 low-speed status for usb port 1 (otg transceiver). o usb_hsten1 host enabled status for usb port 1. o mat1[1] match output for timer 1, channel 1. p1[26]/ usb_sspnd1/ pwm1[6]/ cap0[0] p8 [1] i/o p1[26] general purpose digital input/output pin. o usb_sspnd1 usb port 1 bus suspend status (otg transceiver). o pwm1[6] pulse width modulator 1, channel 6 output. i cap0[0] capture input for timer 0, channel 0. p1[27]/ usb_int1/ usb_o vrcr1/ cap0[1] m9 [1] i/o p1[27] general purpose digital input/output pin. i usb_int1 usb port 1 otg transceiver interrupt. i usb_o vrcr1 usb port 1 over-current status. i cap0[1] capture input for timer 0, channel 1. p1[28]/ usb_scl1/ pcap1[0]/ mat0[0] p10 [1] i/o p1[28] general purpose digital input/output pin. i/o usb_scl1 usb port 1 i 2 c serial clock (otg transceiver). i pcap1[0] capture input for pwm1, channel 0. o mat0[0] match output for timer 0, channel 0. p1[29]/ usb_sda1/ pcap1[1]/ mat0[1] n10 [1] i/o p1[29] general purpose digital input/output pin. i/o usb_sda1 usb port 1 i 2 c serial data (otg transceiver). i pcap1[1] capture input for pwm1, channel 1. o mat0[1] match output for timer 0, channel 0. p1[30]/ usb_pwrd2/ v bus /ad0[4] k3 [2] i/o p1[30] general purpose digital input/output pin. i usb_pwrd2 power status for usb port 2. i v bus monitors the presence of usb bus power. note: this signal must be high for usb reset to occur. i ad0[4] a/d converter 0, input 4. p1[31]/ usb_o vrcr2/ sck1/ad0[5] k2 [2] i/o p1[31] general purpose digital input/output pin. i usb_o vrcr2 over-current status for usb port 2. i/o sck1 serial clock for ssp1. i ad0[5] a/d converter 0, input 5. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 14 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p2[0] to p2[31] i/o port 2: port 2 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 2 pins depends upon the pin function selected via the pin connect block. pins p2[14:15], p2[22:23], p[26:27] and p2[30:31] are not available. p2[0]/pwm1[1]/ txd1/ traceclk d12 [1] i/o p2[0] general purpose digital input/output pin. o pwm1[1] pulse width modulator 1, channel 1 output. o txd1 transmitter output for uart1. o traceclk trace clock. p2[1]/pwm1[2]/ rxd1/ pipestat0 c14 [1] i/o p2[1] general purpose digital input/output pin. o pwm1[2] pulse width modulator 1, channel 2 output. i rxd1 receiver input for uart1. o pipestat0 pipeline status, bit 0. p2[2]/pwm1[3]/ cts1/ pipestat1 e11 [1] i/o p2[2] general purpose digital input/output pin. o pwm1[3] pulse width modulator 1, channel 3 output. i cts1 clear to send input for uart1. o pipestat1 pipeline status, bit 1. p2[3]/pwm1[4]/ dcd1/ pipestat2 e13 [1] i/o p2[3] general purpose digital input/output pin. o pwm1[4] pulse width modulator 1, channel 4 output. i dcd1 data carrier detect input for uart1. o pipestat2 pipeline status, bit 2. p2[4]/pwm1[5]/ dsr1/ tracesync e14 [1] i/o p2[4] general purpose digital input/output pin. o pwm1[5] pulse width modulator 1, channel 5 output. i dsr1 data set ready input for uart1. o tracesync trace synchronization. p2[5]/pwm1[6]/ dtr1/ tracepkt0 f12 [1] i/o p2[5] general purpose digital input/output pin. o pwm1[6] pulse width modulator 1, channel 6 output. o dtr1 data terminal ready output for uart1. o tracepkt0 trace packet, bit 0. p2[6]/pcap1[0]/ri1/ tracepkt1 f13 [1] i/o p2[6] general purpose digital input/output pin. i pcap1[0] capture input for pwm1, channel 0. i ri1 ring indicator input for uart1. o tracepkt1 trace packet, bit 1. p2[7]/rd2/ rts1/ tracepkt2 g11 [1] i/o p2[7] general purpose digital input/output pin. i rd2 can2 receiver input. o rts1 request to send output for uart1. o tracepkt2 trace packet, bit 2. p2[8]/td2/ txd2/ tracepkt3 g14 [1] i/o p2[8] general purpose digital input/output pin. o td2 can2 transmitter output. o txd2 transmitter output for uart2. o tracepkt3 trace packet, bit 3. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 15 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p2[9]/ usb_connect1/ rxd2/ extin0 h11 [1] i/o p2[9] general purpose digital input/output pin. o usb_connect1 usb1 softconnect control. signal used to switch an external 1.5 k w resistor under the software control. used with the softconnect usb feature. i rxd2 receiver input for uart2. i extin0 external trigger input. p2[10]/ eint0 m13 [6] i/o p2[10] general purpose digital input/output pin. note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after a reset. i eint0 external interrupt 0 input. p2[11]/ eint1/ mcidat1/ i2stx_clk m12 [6] i/o p2[11] general purpose digital input/output pin. i eint1 external interrupt 1 input. i/o mcidat1 data line 1 for sd/mmc interface. i/o i2stx_clk transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . p2[12]/ eint2/ mcidat2/ i2stx_ws n14 [6] i/o p2[12] general purpose digital input/output pin. i eint2 external interrupt 2 input. i/o mcidat2 data line 2 for sd/mmc interface. i/o i2stx_ws transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . p2[13]/ eint3/ mcidat3/ i2stx_sda m11 [6] i/o p2[13] general purpose digital input/output pin. i eint3 external interrupt 3 input. i/o mcidat3 data line 3 for sd/mmc interface. i/o i2stx_sda transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . p2[16]/ cas p9 [1] i/o p2[16] general purpose digital input/output pin. o cas low active sdram column address strobe. p2[17]/ ras p11 [1] i/o p2[17] general purpose digital input/output pin. o ras low active sdram row address strobe. p2[18]/ clkout0 p3 [1] i/o p2[18] general purpose digital input/output pin. o clkout0 sdram clock 0. p2[19]/ clkout1 n5 [1] i/o p2[19] general purpose digital input/output pin. o clkout1 sdram clock 1. p2[20]/ d ycs0 p6 [1] i/o p2[20] general purpose digital input/output pin. o d ycs0 sdram chip select 0. p2[21]/ d ycs1 n8 [1] i/o p2[21] general purpose digital input/output pin. o d ycs1 sdram chip select 1. p2[24]/ ckeout0 p1 [1] i/o p2[24] general purpose digital input/output pin. o ckeout0 sdram clock enable 0. p2[25]/ ckeout1 p2 [1] i/o p2[25] general purpose digital input/output pin. o ckeout1 sdram clock enable 1. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 16 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p2[28]/ dqmout0 m2 [1] i/o p2[28] general purpose digital input/output pin. o dqmout0 data mask 0 used with sdram and static devices. p2[29]/ dqmout1 l1 [1] i/o p2[29] general purpose digital input/output pin. o dqmout1 data mask 1 used with sdram and static devices. p3[0] to p3[31] i/o port 3: port 3 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 3 pins depends upon the pin function selected via the pin connect block. pins p3[16:22] and p3[27:31] are not available. p3[0]/d0 d6 [1] i/o p3[0] general purpose digital input/output pin. i/o d0 external memory data line 0. p3[1]/d1 e6 [1] i/o p3[1] general purpose digital input/output pin. i/o d1 external memory data line 1. p3[2]/d2 a2 [1] i/o p3[2] general purpose digital input/output pin. i/o d2 external memory data line 2. p3[3]/d3 g5 [1] i/o p3[3] general purpose digital input/output pin. i/o d3 external memory data line 3. p3[4]/d4 d3 [1] i/o p3[4] general purpose digital input/output pin. i/o d4 external memory data line 4. p3[5]/d5 e3 [1] i/o p3[5] general purpose digital input/output pin. i/o d5 external memory data line 5. p3[6]/d6 f4 [1] i/o p3[6] general purpose digital input/output pin. i/o d6 external memory data line 6. p3[7]/d7 g3 [1] i/o p3[7] general purpose digital input/output pin. i/o d7 external memory data line 7. p3[8]/d8 a6 [1] i/o p3[8] general purpose digital input/output pin. i/o d8 external memory data line 8. p3[9]/d9 a4 [1] i/o p3[9] general purpose digital input/output pin. i/o d9 external memory data line 9. p3[10]/d10 b3 [1] i/o p3[10] general purpose digital input/output pin. i/o d10 external memory data line 10. p3[11]/d11 b2 [1] i/o p3[11] general purpose digital input/output pin. i/o d11 external memory data line 11. p3[12]/d12 a1 [1] i/o p3[12] general purpose digital input/output pin. i/o d12 external memory data line 12. p3[13]/d13 c1 [1] i/o p3[13] general purpose digital input/output pin. i/o d13 external memory data line 13. p3[14]/d14 f1 [1] i/o p3[14] general purpose digital input/output pin. i/o d14 external memory data line 14. p3[15]/d15 g4 [1] i/o p3[15] general purpose digital input/output pin. i/o d15 external memory data line 15. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 17 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p3[23]/cap0[0]/ pcap1[0] m4 [1] i/o p3[23] general purpose digital input/output pin. i cap0[0] capture input for timer 0, channel 0. i pcap1[0] capture input for pwm1, channel 0. p3[24]/cap0[1]/ pwm1[1] n3 [1] i/o p3[24] general purpose digital input/output pin. i cap0[1] capture input for timer 0, channel 1. o pwm1[1] pulse width modulator 1, output 1. p3[25]/mat0[0]/ pwm1[2] m3 [1] i/o p3[25] general purpose digital input/output pin. o mat0[0] match output for timer 0, channel 0. o pwm1[2] pulse width modulator 1, output 2. p3[26]/mat0[1]/ pwm1[3] k7 [1] i/o p3[26] general purpose digital input/output pin. o mat0[1] match output for timer 0, channel 1. o pwm1[3] pulse width modulator 1, output 3. p4[0] to p4[31] i/o port 4: port 4 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 4 pins depends upon the pin function selected via the pin connect block. pins p4[20:23] are not available. p4[0]/a0 l6 [1] i/o p4[0] general purpose digital input/output pin. i/o a0 external memory address line 0. p4[1]/a1 m7 [1] i/o p4[1] general purpose digital input/output pin. i/o a1 external memory address line 1. p4[2]/a2 m8 [1] i/o p4[2] general purpose digital input/output pin. i/o a2 external memory address line 2. p4[3]/a3 k9 [1] i/o p4[3] general purpose digital input/output pin. i/o a3 external memory address line 3. p4[4]/a4 p13 [1] i/o p4[4] general purpose digital input/output pin. i/o a4 external memory address line 4. p4[5]/a5 h10 [1] i/o p4[5] general purpose digital input/output pin. i/o a5 external memory address line 5. p4[6]/a6 k10 [1] i/o p4[6] general purpose digital input/output pin. i/o a6 external memory address line 6. p4[7]/a7 k12 [1] i/o p4[7] general purpose digital input/output pin. i/o a7 external memory address line 7. p4[8]/a8 j11 [1] i/o p4[8] general purpose digital input/output pin. i/o a8 external memory address line 8. p4[9]/a9 h12 [1] i/o p4[9] general purpose digital input/output pin. i/o a9 external memory address line 9. p4[10]/a10 g12 [1] i/o p4[10] general purpose digital input/output pin. i/o a10 external memory address line 10. p4[11]/a11 f11 [1] i/o p4[11] general purpose digital input/output pin. i/o a11 external memory address line 11. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 18 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller p4[12]/a12 f10 [1] i/o p4[12] general purpose digital input/output pin. i/o a12 external memory address line 12. p4[13]/a13 b14 [1] i/o p4[13] general purpose digital input/output pin. i/o a13 external memory address line 13. p4[14]/a14 e8 [1] i/o p4[14] general purpose digital input/output pin. i/o a14 external memory address line 14. p4[15]/a15 c10 [1] i/o p4[15] general purpose digital input/output pin. i/o a15 external memory address line 15. p4[16]/a16 n12 [1] i/o p4[16] general purpose digital input/output pin. i/o a16 external memory address line 16. p4[17]/a17 n13 [1] i/o p4[17] general purpose digital input/output pin. i/o a17 external memory address line 17. p4[18]/a18 p14 [1] i/o p4[18] general purpose digital input/output pin. i/o a18 external memory address line 18. p4[19]/a19 m14 [1] i/o p4[19] general purpose digital input/output pin. i/o a19 external memory address line 19. p4[24]/ oe c8 [1] i/o p4[24] general purpose digital input/output pin. o oe low active output enable signal. p4[25]/ we d9 [1] i/o p4[25] general purpose digital input/output pin. o we low active write enable signal. p4[26]/ bls0 k13 [1] i/o p4[26] general purpose digital input/output pin. o bls0 low active byte lane select signal 0. p4[27]/ bls1 f14 [1] i/o p4[27] general purpose digital input/output pin. o bls1 low active byte lane select signal 1. p4[28]/mat2[0]/ txd3 d10 [1] i/o p4[28] general purpose digital input/output pin. o mat2[0] match output for timer 2, channel 0. o txd3 transmitter output for uart3. p4[29]/mat2[1]/ rxd3 b9 [1] i/o p4[29] general purpose digital input/output pin. o mat2[1] match output for timer 2, channel 1. i rxd3 receiver input for uart3. p4[30]/ cs0 c7 [1] i/o p4[30] general purpose digital input/output pin. o cs0 low active chip select 0 signal. p4[31]/ cs1 e7 [1] i/o p4[31] general purpose digital input/output pin. o cs1 low active chip select 1 signal. alarm h5 [8] o alarm rtc controlled output. this is a 1.8 v pin. it goes high when a rtc alarm is generated. usb_d - 2 n2 i/o usb_d - 2 usb port 2 bidirectional d - line. dbgen e5 [1] i dbgen jtag interface control signal. also used for boundary scan. tdo b1 [1] o tdo test data out for jtag interface. tdi c3 [1] i tdi test data in for jtag interface. tms c2 [1] i tms test mode select for jtag interface. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 19 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis. [2] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input. when con?gured as a adc input, digital section of the pad is disabled. [3] 5 v tolerant pad providing digital i/o with ttl levels and hysteresis and analog output function. when con?gured as the dac o utput, digital section of the pad is disabled. trst d4 [1] i trst test reset for jtag interface. tck d2 [1] i tck test clock for jtag interface. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. rtck c4 [1] i/o rtck jtag interface control signal. note: low on this pin while reset is low enables etm pins (p2[9:0]) to operate as trace port after reset. rst out h2 o rst out this is a 3.3 v pin. low on this pin indicates lpc2458 being in reset state. reset j1 [7] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 l2 [8] i input to the oscillator circuit and internal clock generator circuits. xtal2 k4 [8] o output from the oscillator ampli?er. rtcx1 j2 [8] i input to the rtc oscillator circuit. rtcx2 j3 [8] o output from the rtc oscillator circuit. v ssio h4, p4, l9, l13, g13, d13, c11, b4 [9] i ground: 0 v reference for the digital io pins. v sscore h3, l8, a10 [9] i ground: 0 v reference for the core. v ssa f3 [10] i analog ground: 0 v reference. this should nominally be the same voltage as v ssio /v sscore , but should be isolated to minimize noise and error. v dd(3v3) e2, l4, k8, l11, j14, e12, e10, c5 [11] i 3.3 v supply voltage: this is the power supply voltage for the i/o ports. n.c. h1, l12, g10 [12] i not connected pins: these pins must be left unconnected (?oating). v dd(dcdc)(3v3) g1, n9, e9 [13] i 3.3 v dc-to-dc converter supply voltage: this is the power supply for the on-chip dc-to-dc converter. v dda f2 [14] i analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. vref g2 [14] i adc reference: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. the level on this pin is used as a reference for adc and dac. vbat k1 [14] i rtc power supply: 3.3 v on this pin supplies the power to the rtc peripheral. table 4. pin description continued symbol ball type description
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 20 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller [4] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus 400 khz speci?cation. it requires an external pull-up to provide output functionality. when power is switched off, this pin connected to the i 2 c-bus is ?oating and does not disturb the i 2 c lines. open-drain con?guration applies to all functions on this pin. [5] pad provides digital i/o and usb functions. it is designed in accordance with the usb speci?cation, revision 2.0 (full-speed and low-speed mode only). [6] 5 v tolerant pad with 5 ns glitch ?lter providing digital i/o functions with ttl levels and hysteresis. [7] 5 v tolerant pad with 20 ns glitch ?lter providing digital i/o function with ttl levels and hysteresis. [8] pad provides special analog functionality. [9] pad provides special analog functionality. [10] pad provides special analog functionality. [11] pad provides special analog functionality. [12] pad provides special analog functionality. [13] pad provides special analog functionality. [14] pad provides special analog functionality. 7. functional description 7.1 architectural overview the lpc2458 microcontroller consists of an arm7tdmi-s cpu with emulation support, the arm7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the amba ahb interfacing to high-speed on-chip peripherals and external memory, and the amba apb for connection to other on-chip peripheral functions. the microcontroller permanently con?gures the arm7tdmi-s processor for little-endian byte order. the lpc2458 implements two ahb in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vic, gpdma controller, and emc. the second ahb, referred to as ahb2, includes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into off-chip memory or unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the gpdma function, and the ethernet block (via the bus bridge from ahb2). bus masters with access to ahb2 are the arm7 and the ethernet block. ahb peripherals are allocated a 2 mb range of addresses at the very top of the 4 gb arm memory space. each ahb peripheral is allocated a 16 kb address space within the ahb address space. lower speed peripheral functions are connected to the apb. the ahb to apb bridge interfaces the apb to the ahb. apb peripherals are also allocated a 2 mb range of addresses, beginning at the 3.5 gb address point. each apb peripheral is allocated a 16 kb address space within the apb address space. the arm7tdmi-s processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 21 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set ? a 16-bit thumb set the thumb sets 16-bit instruction length allows it to approach higher density compared to standard arm code while retaining most of the arms performance. 7.2 on-chip ?ash programming memory the lpc2458 incorporates 512 kb ?ash memory system. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in system via the serial port (uart0). the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld and ?rmware upgrades. the ?ash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 mhz. the lpc2458 provides a minimum of 100000 write/erase cycles and 20 years of data retention. 7.3 on-chip sram the lpc2458 includes a sram memory of 64 kb reserved for the arm processor exclusive use. this ram may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. a 16 kb sram block serving as a buffer for the ethernet controller and a 16 kb sram associated with the second ahb can be used both for data and code storage, too. the 2 kb rtc sram can be used for data storage only. the rtc sram is battery powered and retains the content in the absence of the main power supply. 7.4 memory map the lpc2458 memory map incorporates several distinct regions as shown in t ab le 5 and figure 3 . in addition, the cpu interrupt vectors may be remapped to allow them to reside in either ?ash memory (default), boot rom, or sram (see section 7.26.6 ).
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 22 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller table 5. lpc2458 memory usage and details address range general use address range details and description 0x0000 0000 to 0x3fff ffff on-chip non-volatile memory and fast i/o 0x0000 0000 to 0x0007 ffff ?ash memory (512 kb) 0x3fff c000 to 0x3fff ffff fast gpio registers 0x4000 0000 to 0x7fff ffff on-chip ram 0x4000 0000 to 0x4000 ffff ram (64 kb) 0x7fe0 0000 to 0x7fe0 3fff ethernet ram (16 kb) 0x7fd0 0000 to 0x7fd0 3fff usb ram (16 kb) 0x8000 0000 to 0xbfff ffff off-chip memory two static memory banks, 16 mb each 0x8000 0000 to 0x80ff ffff static memory bank 0 0x8100 0000 to 0x81ff ffff static memory bank 1 two dynamic memory banks, 256 mb each 0xa000 0000 to 0xafff ffff dynamic memory bank 0 0xb000 0000 to 0xbfff ffff dynamic memory bank 1 0xe000 0000 to 0xefff ffff apb peripherals 36 peripheral blocks, 16 kb each 0xf000 0000 to 0xffff ffff ahb peripherals
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 23 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.5 interrupt controller the arm processor core has two interrupt inputs called interrupt request (irq) and fast interrupt request (fiq). the vic takes 32 interrupt request inputs which can be programmed as fiq or vectored irq types. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fiqs have the highest priority. if more than one request is assigned to fiq, the vic ors the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq fig 3. lpc2458 memory map 0.0 gb 1.0 gb on-chip non-volatile memory 0x0000 0000 reserved address space special registers on-chip static ram reserved address space 0x4000 0000 0x3fff 8000 0x3fff ffff 2.0 gb 0x8000 0000 0x7fff ffff boot rom and boot flash (boot flash remapped from on-chip flash) 0xdfff ffff 0xc000 0000 0xbfff ffff reserved address space external static and dynamic memory 3.75 gb 4.0 gb 3.5 gb ahb peripherals apb peripherals 0xe000 0000 0xf000 0000 0xffff ffff 002aad657
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 24 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service routine can read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs, which include all interrupt requests that are not classi?ed as fiqs, have a programmable interrupt priority. when more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered vic channel will be serviced ?rst. the vic ors the requests from all of the vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping to the address supplied by that register. 7.5.1 interrupt sources each peripheral device has one interrupt line connected to the vic but may have several interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. such interrupt request coming from port 0 and/or port 2 will be combined with the eint3 interrupt requests. 7.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. 7.7 external memory controller the lpc2458 emc is an arm primecell multiport memory controller peripheral offering support for asynchronous static memory devices such as ram, rom, and ?ash. in addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. the emc is an advanced microcontroller bus architecture (amba) compliant peripheral. 7.7.1 features ? dynamic memory interface support including single data rate sdram. ? asynchronous static memory device support including ram, rom, and ?ash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce latency and to improve performance. ? 8/16 data and 20 address lines wide static memory support. ? 16 bit wide chip select sdram memory support.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 25 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? static memory features include: C asynchronous page mode read C programmable wait states C bus turnaround delay C output enable and write enable delays C extended wait ? two chip selects for synchronous memory and two chip selects for static memory devices. ? power-saving modes dynamically control cke and clkout to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2048 (a0 to a10), 4096 (a0 to a11), and 8192 (a0 to a12) row address synchronous memory parts. that is typical 512 mb, 256 mb, and 128 mb parts, with 4, 8, and 16 data bits per device. ? separate reset domains allow auto-refresh through a chip reset if desired. note: synchronous static memory devices (synchronous burst mode) are not supported. 7.8 general purpose dma controller the gpdma is an amba ahb compliant peripheral allowing selected lpc2458 peripherals to have dma support. the gpdma enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfers for a single source and destination. for example, a bidirectional port requires one stream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the ahb master. 7.8.1 features ? two dma channels. each channel can support a unidirectional transfer. ? the gpdma can transfer data between the 16 kb sram, external memory, and peripherals such as the sd/mmc, two ssps, and the i 2 s interface. ? single dma and burst dma request signals. each peripheral connected to the gpdma can assert either a burst dma request or a single dma request. the dma burst size is set by programming the gpdma. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not have to occupy contiguous areas of memory. ? hardware dma channel priority. each dma channel has a speci?c hardware priority. dma channel 0 has the highest priority and channel 1 has the lowest priority. if requests from two channels become active at the same time, the channel with the highest priority is serviced ?rst. ? ahb slave dma programming interface. the gpdma is programmed by writing to the dma control registers over the ahb slave interface.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 26 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? one ahb master for transferring data. this interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more ef?ciently transfer data. usually the burst size is set to half the size of the fifo in the peripheral. ? internal four-word fifo per channel. ? supports 8-bit, 16-bit, and 32-bit wide transactions. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? interrupt masking. the dma error and dma terminal count interrupt requests can be masked. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.9 fast general purpose parallel i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. lpc2458 use accelerated gpio functions: ? gpio registers are relocated to the arm local bus so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. additionally, any pin on port 0 and port 2 (total of 64 pins) that is not con?gured as an analog input/output can be programmed to generate an interrupt on a rising edge, a falling edge, or both. the edge detection is asynchronous, so it may operate when clocks are not present such as during power-down mode. each enabled interrupt can be used to wake the chip up from power-down mode. 7.9.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? backward compatibility with other earlier devices is maintained with legacy port 0 and port 1 registers appearing at the original addresses on the apb.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 27 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.10 ethernet the ethernet block contains a full featured 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performance through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, ?ow control, control frames, hardware acceleration for transmit retry, receive packet ?ltering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block and the cpu share a dedicated ahb subsystem that is used to access the ethernet sram for ethernet data, control, and status information. all other ahb traf?c in the lpc2458 takes place on a different ahb subsystem, effectively separating ethernet activity from the rest of the system. the ethernet dma can also access off-chip memory via the emc, as well as the sram located on another ahb. however, using memory other than the ethernet sram, especially off-chip memory, will slow ethernet access to memory and increase the loading of its ahb. the ethernet block interfaces between an off-chip ethernet phy using the media independent interface (mii) or reduced mii (rmii) protocol and the on-chip media independent interface management (miim) serial bus. 7.10.1 features ? ethernet standards support: C supports 10 mbit/s or 100 mbit/s phy devices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. C fully compliant with ieee standard 802.3. C fully compliant with 802.3x full duplex ?ow control and half duplex back pressure. C flexible transmit and receive frame options. C virtual local area network (vlan) frame support. ? memory management: C independent transmit and receive buffers memory mapped to shared sram. C dma managers with scatter/gather dma and arrays of frame descriptors. C memory traf?c optimized by buffering and pre-fetching. ? enhanced ethernet features: C receive ?ltering. C multicast and broadcast frame support for both transmit and receive. C optional automatic frame check sequence (fcs) insertion with circular redundancy check (crc) for transmit. C selectable automatic transmit frame padding. C over-length frame support for both transmit and receive allows any length frames. C promiscuous receive mode. C automatic collision back-off and frame retransmission. C includes power management by clock switching. C wake-on-lan power management support allows system wake-up: using the receive ?lters or a magic frame detection ?lter.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 28 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? physical interface: C attachment of external phy chip through standard mii or rmii interface. C phy register access is available via the miim interface. 7.11 usb interface the universal serial bus (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot plugging and dynamic con?guration of the devices. all transactions are initiated by the host controller. the lpc2458 usb interface includes a device, host, and otg controller. details on typical usb interfacing solutions can be found in section 11.1 suggested usb interf ace solutions on page 56 7.11.1 usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, endpoint buffer memory, and a dma controller. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. when enabled, the dma controller transfers data between the endpoint buffer and the usb ram. 7.11.1.1 features ? fully compliant with usb 2.0 speci?cation (full speed). ? supports 32 physical (16 logical) endpoints with a 4 kb endpoint buffer ram. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum speci?cation) by software at run time. ? supports softconnect and goodlink features. ? while usb is in the suspend mode, lpc2458 can enter one of the reduced power modes and wake up on usb activity. ? supports dma transfers with the dma ram of 16 kb on all non-control endpoints. ? allows dynamic switching between cpu-controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 7.11.2 usb host controller the host controller enables full- and low-speed data exchange with usb devices attached to the bus. it consists of a register interface, a serial interface engine and a dma controller. the register interface complies with the ohci speci?cation. 7.11.2.1 features ? ohci compliant.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 29 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? two downstream ports. ? supports per-port power switching. 7.11.3 usb otg controller usb otg is a supplement to the usb 2.0 speci?cation that augments the capability of existing mobile devices and usb peripherals by adding host functionality for connection to usb peripherals. the otg controller integrates the host controller, device controller, and a master-only i 2 c interface to implement otg dual-role device functionality. the dedicated i 2 c interface controls an external otg transceiver. 7.11.3.1 features ? fully compliant with on-the-go supplement to the usb 2.0 speci?cation, revision 1.0a . ? hardware support for host negotiation protocol (hnp). ? includes a programmable timer required for hnp and session request protocol (srp). ? supports any otg transceiver compliant with the otg transceiver speci?cation (cea-2011), rev. 1.0 . 7.12 can controller and acceptance ?lters the controller area network (can) is a serial communications protocol which ef?ciently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed networks to low cost multiplex wiring. the can block is intended to support multiple can buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of can buses in industrial or automotive applications. each can controller has a register structure similar to the nxp sja1000 and the pelican library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the arm environment. the main operational difference is that the recognition of received identi?ers, known in can terminology as acceptance filtering, has been removed from the can controllers and centralized in a global acceptance filter. 7.12.1 features ? two can controllers and buses. ? data rates to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can speci?cation 2.0b, iso 11898-1 . ? global acceptance filter recognizes 11-bit and 29-bit receive identi?ers for all can buses. ? acceptance filter can provide fullcan-style automatic reception for selected standard identi?ers. ? full can messages can generate interrupts.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 30 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.13 10-bit adc the lpc2458 contains one adc. it is a single 10-bit successive approximation adc with eight channels. 7.13.1 features ? 10-bit successive approximation adc ? input multiplexing among 8 pins ? power-down mode ? measurement range 0 v to v i(vref) ? 10-bit conversion time 3 2.44 m s ? burst conversion mode for single or multiple inputs ? optional conversion on transition of input pin or timer match signal ? individual result registers for each adc channel to reduce interrupt overhead 7.14 10-bit dac the dac allows the lpc2458 to generate a variable analog output. the maximum output value of the dac is v i(vref) . 7.14.1 features ? 10-bit dac ? resistor string architecture ? buffered output ? power-down mode ? selectable output drive 7.15 uarts the lpc2458 contains four uarts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface. the uarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.15.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software ?ow control implementation. ? uart1 equipped with standard modem interface signals. this module also provides full support for hardware ?ow control (auto-cts/rts).
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 31 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? uart3 includes an irda mode to support infrared communication. 7.16 spi serial i/o controller the lpc2458 contains one spi controller. spi is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.16.1 features ? compliant with spi speci?cation ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer 7.17 ssp serial i/o controller the lpc2458 contains two ssp controllers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data ?owing from the master to the slave and from the slave to the master. in practice, often only one of these data ?ows carries meaningful data. 7.17.1 features ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? maximum spi bus data bit rate of one half (master mode) and one twelfth (slave mode) of the input clock rate ? dma transfers supported by gpdma 7.18 sd/mmc card interface the secure digital and multimedia card interface (mci) allows access to external sd memory cards. the sd card interface conforms to the sd multimedia card speci?cation version 2.11 . 7.18.1 features ? the mci interface provides all functions speci?c to the sd/mmc memory card. these include the clock generation unit, power management control, and command and data transfer.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 32 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? conforms to multimedia card speci?cation v2.11 . ? conforms to secure digital memory card physical layer speci?cation, v0.96. ? can be used as a multimedia card bus or a secure digital memory card bus host. the sd/mmc can be connected to several multimedia cards or a single secure digital memory card. ? dma supported through the gpdma controller. 7.19 i 2 c-bus serial i/o controller the lpc2458 contains three i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as memory). transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus and can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in lpc2458 supports bit rates up to 400 kbit/s (fast i 2 c-bus). 7.19.1 features ? i 2 c0 is a standard i 2 c compliant bus interface with open-drain pins. ? i 2 c1 and i 2 c2 use standard i/o pins and do not support powering off of individual devices connected to the same bus lines. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. 7.20 i 2 s-bus serial i/o controllers the i 2 s-bus provides a standard communication interface for digital audio applications. the i 2 s-bus speci?cation de?nes a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s interface on the lpc2458 provides a separate transmit and receive channel, each of which can operate as either a master or a slave.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 33 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.20.1 features ? the interface has separate input/output channels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 48 khz (16, 22.05, 32, 44.1, 48) khz. ? con?gurable word select period in master mode (separately for i 2 s input and output). ? two 8 word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programmable buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s input and i 2 s output. 7.21 general purpose 32-bit timers/external event counters the lpc2458 includes four 32-bit timer/counters. the timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. it can optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. the timer/counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.21.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 34 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.22 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc2458. the timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when speci?ed timer values occur, based on seven match registers. the pwm function is in addition to these features and is based on match register events. the ability to separately control rising and falling edge locations allows the pwm to be used for more applications. for instance, multi-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. a dedicated match register controls the pwm cycle rate, by resetting the count upon match. the other match register controls the pwm edge position. additional single edge controlled pwm outputs require only one match register each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an pwmmr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, a dedicated match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, speci?c match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). 7.22.1 features ? lpc2458 has two pwms with the same operational features. these may be operated in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. pwm0 acts as the master and pwm1 as the slave for this use. ? counter or timer operation (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to 6 single edge controlled or 3 double edge controlled pwm outputs, or a mix of both types. the match registers also allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 35 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? pulse period and width can be any number of timer counts. this allows complete ?exibility in the trade-off between resolution and repetition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. software must release new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 7.23 watchdog timer (wdt) the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 7.23.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) 256 4) to (t cy(wdclk) 2 32 4) in multiples of t cy(wdclk) 4. ? the watchdog clock (wdclk) source can be selected from the rtc clock, the internal rc oscillator (irc), or the apb peripheral clock. this gives a wide range of potential timing choices of watchdog operation under different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability. 7.24 rtc and battery ram the rtc is a set of counters for measuring time when system power is on, and optionally when power is off. it uses little power in power-down mode. on the lpc2458, the rtc can be clocked by a separate 32.768 khz oscillator or by a programmable prescale divider based on the apb clock. also, the rtc is powered by its own power supply pin, vbat, which can be connected to a battery or to the same 3.3 v supply used by the rest of the device.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 36 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, which can be supplied by an external battery. when the cpu and the rest of chip functions are stopped and power is removed, the rtc can supply an alarm output that can be used by external hardware to restore chip power and resume operation. 7.24.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? dedicated 32 khz oscillator or programmable prescaler from apb clock. ? dedicated power supply pin can be connected to a battery or to the main 3.3 v. ? an alarm output pin is included to assist in waking up when the chip has had power removed to all functions except the rtc and battery ram. ? periodic interrupts can be generated from increments of any ?eld of the time registers, and selected fractional second values. this enhancement enables the rtc to be used as a system timer. ? 2 kb data sram powered by vbat. ? rtc and battery ram power supply is isolated from the rest of the chip. 7.25 clocking and power control 7.25.1 crystal oscillators the lpc2458 includes three independent oscillators. these are the main oscillator, the internal rc oscillator, and the rtc oscillator. each oscillator can be used for more than one purpose as required in a particular application. any of the three clock sources can be chosen by software to drive the pll and ultimately the cpu. following reset, the lpc2458 will operate from the internal rc oscillator until switched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. 7.25.1.1 internal rc oscillator the irc may be used as the clock source for the wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 4 mhz. the irc is trimmed to 1 % accuracy. upon power-up or any chip reset, the lpc2458 uses the irc as the clock source. software may later switch to one of the other available clock sources. 7.25.1.2 main oscillator the main oscillator can be used as the clock source for the cpu, with or without using the pll. the main oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the pll. the clock selected as the pll input is pllclkin. the arm processor clock frequency is referred to as cclk elsewhere in this document. the frequencies of
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 37 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller pllclkin and cclk are the same value unless the pll is active and connected. the clock frequency for each peripheral can be selected individually and is referred to as pclk. refer to section 7.25.2 for additional information. 7.25.1.3 rtc oscillator the rtc oscillator can be used as the clock source for the rtc and/or the wdt. also, the rtc oscillator can be used to drive the pll and the cpu. 7.25.2 pll the pll accepts an input clock frequency in the range of 32 khz to 25 mhz. the input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the cpu and the usb block. the pll input, in the range of 32 khz to 25 mhz, may initially be divided down by a value n, which may be in the range of 1 to 256. this input division provides a wide range of output frequencies from the same input frequency. following the pll input divider is the pll multiplier. this can multiply the input divider output through the use of a current controlled oscillator (cco) by a value m, in the range of 1 through 32768. the resulting frequency must be in the range of 275 mhz to 550 mhz. the multiplier works by dividing the cco output by the value of m, then using a phase-frequency detector to compare the divided cco output to the multiplier input. the error value is used to adjust the cco frequency. the pll is turned off and bypassed following a chip reset and by entering power-down mode. pll is enabled by software only. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. 7.25.3 wake-up timer the lpc2458 begins operation at power-up and when awakened from power-down mode by using the 4 mhz irc oscillator as the clock source. this allows chip operation to resume quickly. if the main oscillator or the pll is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. when the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. when power is applied to the chip, or when some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(3v3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 38 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.25.4 power control the lpc2458 supports a variety of power control features. there are three special modes of processor power reduction: idle mode, sleep mode, and power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, recon?guring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing ?ne tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. each of the peripherals has its own clock divider which provides even better power control. the lpc2458 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the rtc and a small sram, referred to as the battery ram. 7.25.4.1 idle mode in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.25.4.2 sleep mode in sleep mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout sleep mode and the logic levels of chip pins remain static. the output of the irc is disabled but the irc is not powered down for a fast wake-up later. the 32 khz rtc oscillator is not stopped because the rtc interrupts may be used as the wake-up source. the pll is automatically turned off and disconnected. the cclk and usb clock dividers automatically get reset to zero. the sleep mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, sleep mode reduces chip power consumption to a very low value. the ?ash memory is left on in sleep mode, allowing a very quick wake-up. on the wake-up from sleep mode, if the irc was used before entering sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. if the main external oscillator was used, the code execution will resume when 4096 cycles expire. the customers need to recon?gure the pll and clock dividers accordingly. 7.25.4.3 power-down mode power-down mode does everything that sleep mode does, but also turns off the irc oscillator and the ?ash memory. this saves more power, but requires waiting for resumption of ?ash operation before execution of code or data access in the ?ash memory can be accomplished. on the wake-up from power-down mode, if the irc was used before entering power-down mode, it will take irc 60 m s to start-up. after this 4 irc cycles will expire before the code execution can then be resumed if the code was running from sram. in the meantime, the
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 39 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ?ash wake-up timer then counts 4 mhz irc clock cycles to make the 100 m s ?ash start-up time. when it times out, access to the ?ash will be allowed. the customers need to recon?gure the pll and clock dividers accordingly. 7.25.4.4 power domains the lpc2458 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the battery ram. on the lpc2458, i/o pads are powered by the 3.3 v (v dd(3v3) ) pins, while the v dd(dcdc)(3v3) pins power the on-chip dc-to-dc converter which in turn provides power to the cpu and most of the peripherals. although both the i/o pad ring and the core require a 3.3 v supply, different powering schemes can be used depending on the actual application requirements. the ?rst option assumes that power consumption is not a concern and the design ties the v dd(3v3) and v dd(dcdc)(3v3) pins together. this approach requires only one 3.3 v power supply for both pads, the cpu, and peripherals. while this solution is simple, it does not support powering down the i/o pad ring on the ?y while keeping the cpu and peripherals alive. the second option uses two power supplies; a 3.3 v supply for the i/o pads (v dd(3v3) ) and a dedicated 3.3 v supply for the cpu (v dd(dcdc)(3v3) ). having the on-chip dc-dc converter powered independently from the i/o pad ring enables shutting down of the i/o pad power supply on the ?y, while the cpu and peripherals stay active. the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, which can be supplied by an external battery. when the cpu and the rest of chip functions are stopped and power removed, the rtc can supply an alarm output that may be used by external hardware to restore chip power and resume operation. 7.26 system control 7.26.1 reset reset has four sources on the lpc2458: the reset pin, the watchdog reset, power-on reset, and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 7.25.3 w ak e-up timer ), causing reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the ?ash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. at that point, all of the processor and peripheral registers have been initialized to predetermined values.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 40 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 7.26.2 brownout detection the lpc2458 includes 2-stage monitoring of the voltage on the v dd(3v3) pins. if this voltage falls below 2.95 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt in the interrupt enable register in the vic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register. the second stage of low-voltage detection asserts reset to inactivate the lpc2458 when the voltage on the v dd(3v3) pins falls below 2.65 v. this reset prevents alteration of the ?ash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the 2.95 v and 2.65 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.95 v detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 7.26.3 code security (code read protection - crp) this feature of the lpc2458 allows user to enable different levels of security in the system so that access to the on-chip ?ash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a speci?c pattern into a dedicated ?ash location. iap commands are not affected by the crp. there are three levels of the code read protection. crp1 disables access to chip via the jtag and allows partial ?ash update (excluding ?ash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and ?ash ?eld updates are needed but all sectors can not be erased. crp2 disables access to chip via the jtag and only allows full ?ash erase and update using a reduced set of the isp commands. running an application with level crp3 selected fully disables any access to chip via the jtag pins and the isp. this mode effectively disables isp override using p2[10] pin, too. it is up to the users application to provide (if needed) ?ash update mechanism using iap calls or call reinvoke isp command to enable ?ash update via uart0. 7.26.4 ahb the lpc2458 implements two ahb in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vectored interrupt controller, gpdma controller, usb interface, and 16 kb sram. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 41 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller the second ahb, referred to as ahb2, includes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into off-chip memory or unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the usb block, the gpdma function, and the ethernet block (via the bus bridge from ahb2). bus masters with access to ahb2 are the arm7 and the ethernet block. 7.26.5 external interrupt inputs the lpc2458 includes up to 68 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 7.26.6 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. vectors may be mapped to the bottom of the boot rom, the sram, or external memory. this allows code running in different memory spaces to have control of the interrupts. 7.27 emulation and debugging the lpc2458 support emulation and debugging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on p2[0] to p2[9]. this means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself. 7.27.1 embeddedice the embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. the embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm7tdmi-s core present on the target system. the arm core has a debug communication channel (dcc) function built-in. the dcc allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even entering the debug state. the dcc is accessed as a coprocessor 14 by the program running on the arm7tdmi-s core. the dcc allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the dcc data and control registers are mapped in to addresses in the embeddedice logic. the jtag clock (tck) must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. 7.27.2 embedded trace since the lpc2458 have signi?cant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. the etm provides real-time trace capability for deeply embedded processor cores. it outputs
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 42 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller information about processor execution to a trace port. a software debugger allows con?guration of the etm using a jtag interface and displays the trace information that has been captured. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer captures the trace information under software debugger control. the trace port can broadcast the instruction trace information. instruction trace (or pc trace) shows the ?ow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is signi?cantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code can not be traced because of this restriction. 7.27.3 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real-time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc, which is present in the embeddedice logic. the lpc2458 contain a speci?c con?guration of realmonitor software programmed into the on-chip rom memory.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 43 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ssio /v sscore unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. [6] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.6 v v dda analog 3.3 v pad supply voltage - 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc - 0.5 +4.6 v v i(vref) input voltage on pin vref - 0.5 +4.6 v v ia analog input voltage on adc related pins - 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(3v3) supply voltage is present [2] - 0.5 +6.0 v other i/o pins [2] [3] - 0.5 v dd(3v3) + 0.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma t stg storage temperature [5] - 65 +150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model; all pins [6] - 2000 +2000 v
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 44 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 9. static characteristics table 7. static characteristics t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.3 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 3.0 3.3 3.6 v v i(vbat) input voltage on pin vbat [2] 2.0 3.3 3.6 v v i(vref) input voltage on pin vref 2.5 3.3 v dda v standard port pins, reset, rtck i il low-level input current v i = 0 v; no pull-up - - 3 m a i ih high-level input current v i =v dd(3v3) ; no pull-down - - 3 m a i oz off-state output current v o =0v; v o =v dd(3v3) ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 c - - 100 ma v i input voltage pin con?gured to provide a digital function [3] [4] [5] [6] 0 - 5.5 v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = - 4 ma [7] v dd(3v3) - 0.4 --v v ol low-level output voltage i ol = - 4 ma [7] - - 0.4 v i oh high-level output current v oh =v dd(3v3) - 0.4 v [7] - 4- - ma i ol low-level output current v ol = 0.4 v [7] 4- - ma i ohs high-level short-circuit output current v oh =0v [8] -- - 45 ma i ols low-level short-circuit output current v ol =v dda [8] --50ma i pd pull-down current v i =5v [9] 10 50 150 m a i pu pull-up current v i =0v - 15 - 50 - 85 m a v dd(3v3) lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 45 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller i dd(dcdc)act(3v3) active mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb =25 c; code while(1){} executed from ?ash; no peripherals enabled; pclk = cclk cclk = 10 mhz - 15 - ma cclk = 72 mhz - 63 - ma all peripherals enabled; pclk = cclk / 8 cclk = 10 mhz - 21 - ma cclk = 72 mhz - 92 - ma all peripherals enabled; pclk = cclk cclk = 10 mhz - 27 - ma cclk = 72 mhz - 125 - ma i dd(dcdc)pd(3v3) power-down mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb =25 c - 150 - m a i batact active mode battery supply current dc-to-dc converter on [10] -20- m a dc-to-dc converter off [10] -28- m a i 2 c-bus pins (p0[27] and p0[28]) v ih high-level input voltage 0.7v dd(3v3) --v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage - 0.5v dd(3v3) -v v ol low-level output voltage i ols = 3 ma [7] - - 0.4 v i li input leakage current v i =v dd(3v3) [11] -24 m a v i =5v - 10 22 m a oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v v o(xtal2) output voltage on pin xtal2 0 - 1.8 v v i(rtcx1) input voltage on pin rtcx1 0 - 1.8 v v o(rtcx2) output voltage on pin rtcx2 0 - 1.8 v usb pins i oz off-state output current 0v lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 46 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages [2] the rtc typically fails when v i(vbat) drops below 1.6 v. [3] including voltage on outputs in 3-state mode. [4] v dd(3v3) supply voltages must be present. [5] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. [6] please also see the errata note mentioned in errata sheet. [7] accounts for 100 mv voltage drop in all supply lines. [8] allowed as long as the current limit does not exceed the maximum current allowed by the device. [9] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [10] on pin vbat. [11] to v ssio . [12] includes external resistors of 18 w 1 % on d+ and d - . v di differential input sensitivity | (d+) - (d - ) | 0.2 - - v v cm differential common mode voltage range includes v di range 0.8 - 2.5 v v th(rs)se single-ended receiver switching threshold voltage 0.8 - 2.0 v v ol low-level output voltage for low-/full-speed r l of 1.5 k w to 3.6 v - - 0.18 v v oh high-level output voltage (driven) for low-/full-speed r l of 15 k w to gnd 2.8 - 3.5 v c trans transceiver capacitance pin to gnd - - 20 pf z drv driver output impedance for driver which is not high-speed capable with 33 w series resistor; steady state drive [12] 36 - 44.1 w r pu pull-up resistance softconnect = on 1.1 - 1.9 k w table 7. static characteristics continued t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 47 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller [1] conditions: v ssa =0v, v dda = 3.3 v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 4 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 4 . [5] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 4 . [6] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 4 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 4 . [8] see figure 5 . table 8. adc static characteristics v dda = 2.5 v to 3.6 v; t amb = - 40 c to +85 c unless otherwise speci?ed; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] -- 1 lsb e l(adj) integral non-linearity [1] [4] -- 2 lsb e o offset error [1] [5] -- 3 lsb e g gain error [1] [6] -- 0.5 % e t absolute error [1] [7] -- 4 lsb r vsi voltage source interface resistance [8] --40k w
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 48 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 4. adc characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 49 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 5. suggested adc interface - lpc2458 ad0[y] pin lpc2xxx ad0[y] sample ad0[y] 20 k w 3 pf 5 pf r vsi v ssio, v sscore v ext 002aad586
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 50 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 10. dynamic characteristics [1] characterized but not implemented as production test. guaranteed by design. [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. table 9. dynamic characteristics of usb pins (full-speed) c l = 50 pf; r pu = 1.5 k w on d+ to v dd(3v3) ,unless otherwise speci?ed. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f - - 109 % v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 7 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 7 - 2 - +5 ns t jr1 receiver jitter to next transition - 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % - 9 - +9 ns t eopr1 eop width at receiver must reject as eop; see figure 7 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 7 [1] 82 --ns table 10. dynamic characteristics t amb = - 40 c to +85 c for commercial applications; v dd(3v3) over speci?ed ranges. [1] symbol parameter conditions min typ [2] max unit external clock f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 42 - 1000 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns i 2 c-bus pins (p0[27] and p0[28]) t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns ssp interface t su(spi_miso) spi_miso set-up time t amb =25 c; measured in spi master mode; see figure 8 -11-ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 51 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller table 11. dynamic characteristics: static external memory interface c l =30pf, t amb = - 40 c to 85 c, v dd(dcdc)(3v3) = v dd(3v3) = 3.0 v to 3.6 v, ahb clock = 1 mhz symbol parameter conditions min typ max unit common to read and write cycles [1] t cslav cs low to address valid time - 0.29 0.20 2.54 ns read cycle parameters [1] [2] t oelav oe low to address valid time - 0.29 0.20 2.54 ns t csloel cs low to oe low time - 0.78 + t cy(cclk) waitoen 0 + t cy(cclk) waitoen 0.49 + t cy(cclk) waitoen ns t am memory access time [3] [4] (waitrd - waitoen + 1) t cy(cclk) - 8.11 (waitrd - waitoen + 1) t cy(cclk) - 9.57 (waitrd - waitoen + 1) t cy(cclk) - 12.70 ns t h(d) data input hold time [5] 1.29 4.22 5.20 ns t cshoeh cs high to oe high time - 0.49 0 0.20 ns t oehanv oe high to address invalid time - 0.20 0.20 2.44 ns t oeloeh oe low to oe high time - 0.59 + (waitrd - waitoen + 1) t cy(cclk) 0 + (waitrd - waitoen + 1) t cy(cclk) 0.10 + (waitrd - waitoen + 1) t cy(cclk) t blslav bls low to address valid time - 0.39 0 2.54 ns t cshblsh cs high to bls high time - 0.88 0.49 0.68 ns write cycle parameters [1] [6] t cslwel cs low to we low time - 0.88 + t cy(cclk) (1 + waitwen) 0.10 + t cy(cclk) (1 + waitwen) 0.20 + t cy(cclk) (1 + waitwen) ns t cslblsl cs low to bls low time - 0.88 0.49 0.98 ns t weldv we low to data valid time 0.68 2.54 5.86 ns t csldv cs low to data valid time 0 2.64 4.79 ns t welweh we low to we high time [3] - 0.78 + t cy(cclk) (waitwr - waitwen + 1) 0 + t cy(cclk) (waitwr - waitwen + 1) 0.10 + t cy(cclk) (waitwr - waitwen + 1) ns t blslblsh bls low to bls high time [3] - 0.88 + t cy(cclk) (waitwr - waitwen + 3) 0 + t cy(cclk) (waitwr - waitwen + 3) 0.59 + t cy(cclk) (waitwr - waitwen + 3) ns t wehanv we high to address invalid time [3] 0 + t cy(cclk) 0.20 + t cy(cclk) 2.74 + t cy(cclk) ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 52 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller [1] v oh = 2.5 v, v ol = 0.2 v. [2] v ih = 2.5 v, v il = 0.5 v. [3] t cy(cclk) = 1 cclk . [4] latest of address valid, cs low, oe low to data valid. [5] earliest of cs high, oe high, address change to data invalid. [6] byte lane state bit (pb) = 1. t wehdnv we high to data invalid time [3] 0.78 2.54 5.96 ns t blshanv bls high to address invalid time [3] - 0.29 0.20 2.54 ns t blshdnv bls high to data invalid time [3] 0 2.54 5.37 ns table 11. dynamic characteristics: static external memory interface continued c l =30pf, t amb = - 40 c to 85 c, v dd(dcdc)(3v3) = v dd(3v3) = 3.0 v to 3.6 v, ahb clock = 1 mhz symbol parameter conditions min typ max unit
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 53 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller table 12. dynamic characteristics: dynamic external memory interface c l =30pf, t amb = - 40 c to 85 c, v dd(dcdc)(3v3) = v dd(3v3) = 3.0 v to 3.6 v, ahb clock = 1 mhz symbol parameter conditions min typ max unit common t d(sv) chip select valid delay time - 1.05 1.76 ns t h(s) chip select hold time 0.1 1.02 - ns t d(rasv) row address strobe valid delay time - 1.51 1.95 ns t h(ras) row address strobe hold time 0.5 1.51 - ns t d(casv) column address strobe valid delay time - 0.98 1.27 ns t h(cas) column address strobe hold time 0.1 0.97 - ns t d(wv) write valid delay time - 0.84 1.95 ns t h(w) write hold time 0.1 0.84 - ns t d(gv) output enable valid delay time - 0.95 1.86 ns t h(g) output enable hold time 0.1 1 - ns t d(av) address valid delay time - 0.87 1.95 ns t h(a) address hold time 0.1 0.81 - ns read cycle parameters t su(d) data input set-up time 0.51 2.24 - ns t h(d) data input hold time 0.57 2.41 - ns write cycle parameters t d(qv) data output valid delay time - 2.65 4.36 ns t h(q) data output hold time 0.49 2.61 - ns
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 54 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 10.1 timing fig 6. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 fig 7. differential data-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop fig 8. miso line set-up time in ssp master mode t su(spi_miso) sck shifting edges mosi miso 002aad326 sampling edges
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 55 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 9. external memory read access cs addr data oe bls t cslav t oelav t oeloeh t csloel t am t h(d) t cshoeh t oehanv 002aad955 t blslav t cshblsh fig 10. external memory write access addr data bls/we oe t cslwel t cslblsl t weldv t csldv t welweh t blslblsh t wehanv t blshanv t wehdnv t blshdnv 002aad956 t avcsl cs
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 56 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 11. application information 11.1 suggested usb interface solutions fig 11. signal timing 002aad636 reference clock output signal (o) input signal (i) t d(xxx) t h(xxx) t h(d) t su(d) fig 12. lpc2458 usb interface on a self-powered device lpc24xx usb-b connector usb_d+ usb_connect soft-connect switch usb_d - v bus v ssio, v sscore v dd(3v3) r1 1.5 k w r s = 33 w 002aad587 r s = 33 w usb_up_led
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 57 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 13. lpc2458 usb interface on a bus-powered device lpc24xx v dd(3v3) r1 1.5 k w r2 usb_up_led 002aad588 usb-b connector usb_d+ usb_d - v bus v ssio, v sscore r s = 33 w r s = 33 w
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 58 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 14. lpc2458 usb otg port con?guration: usb port 1 otg dual-role device, usb port 2 host usb_up_led1 usb_d+1 usb_d - 1 usb_pwrd2 usb_sda1 usb_scl1 rstout 15 k w 15 k w lpc24xx usb-a connector mini-ab connector 33 w 33 w 33 w 33 w v dd v dd v dd usb_up_led2 v dd usb_ovrcr2 lm3526-l ena in 5 v outa flaga v dd d+ d - v bus usb_ppwr2 usb_d+2 usb_d - 2 002aad589 r7 r4 r5 r6 r1 r2 r3 r4 r8 usb_int1 reset_n adr/psw speed suspend oe_n/int_n scl sda int_n v bus id dp dm isp1301 v ssio, v sscore v ssio, v sscore
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 59 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 15. lpc2458 usb otg port con?guration: vp_vm mode usb_tx_dp1 usb_tx_dm1 usb_rcv1 usb_rx_dp1 usb_rx_dm1 usb_scl1 usb_sda1 speed adr/psw sda scl reset_n int_n vp vm suspend oe_n/int_n se0_vm dat_vp rcv v bus id dp dm lpc24xx isp1301 usb mini-ab connector 33 w 33 w 002aad590 usb_tx_e1 rstout v dd v dd usb_int1 usb_up_led1 v dd v ssio, v sscore
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 60 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 16. lpc2458 usb otg port con?guration: usb port 2 device, usb port 1 host usb_up_led1 usb_d+1 usb_d - 1 usb_pwrd1 15 k w 15 k w lpc24xx usb-a connector usb-b connector 33 w 33 w 33 w 33 w 002aad595 v dd usb_up_led2 usb_connect2 v dd v dd usb_ovrcr1 usb_ppwr1 lm3526-l ena in 5 v flaga outa v dd d+ d - d+ d - v bus usb_d+2 usb_d - 2 v bus v bus v ssio, v sscore v ssio, v sscore
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 61 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller fig 17. lpc2458 usb otg port con?guration: usb port 1 host, usb port 2 host usb_up_led1 usb_d+1 usb_d - 1 usb_pwrd1 usb_pwrd2 15 k w 15 k w 15 k w 15 k w lpc24xx usb-a connector usb-a connector 33 w 33 w 33 w 33 w 002aad596 v dd usb_up_led2 v dd usb_ovrcr1 usb_ovrcr2 usb_ppwr1 lm3526-l ena enb in 5 v flaga outa outb flagb v dd v dd d+ d - d+ d - v bus v bus usb_ppwr2 usb_d+2 usb_d - 2 v ssio, v sscore v ssio, v sscore
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 62 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 12. package outline fig 18. package outline sot570-2 (tfbga180) 0.8 a 1 b a 2 unit d y e references outline version european projection issue date 03-03-03 06-03-14 iec jedec jeita mm 1.2 0.35 0.25 0.85 0.75 12.2 11.8 y 1 12.2 11.8 0.5 0.4 0.12 0.1 e 1 10.4 e 2 10.4 dimensions (mm are the original dimensions) sot570-2 e 0.15 v 0.08 w 0 5 10 mm scale sot570-2 tfbga180: thin fine-pitch ball grid array package; 180 balls; body 12 x 12 x 0.8 mm a max. a a 2 a 1 detail x e e x d e a b c d e f h g j k l m n p 246 9 8 1357 10 1314 12 11 b a e 2 e 1 ball a1 index area ball a1 index area 1/2 e 1/2 e y y 1 c b c a c c b ? v m ? w m
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 63 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 13. abbreviations table 13. acronym list acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dcc debug communication channel dma direct memory access eop end of packet etm embedded trace macrocell gpio general purpose input/output irda infrared data association jtag joint test action group mii media independent interface ohc open host controller ohci open host controller interface otg on-the-go phy physical layer pll phase-locked loop pwm pulse width modulator rmii reduced media independent interface sd/mmc secure digital/multimediacard se0 single ended zero spi serial peripheral interface ssi synchronous serial interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 64 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 14. revision history table 14. revision history document id release date data sheet status change notice supersedes lpc2458_2 20081125 product data sheet - lpc2458_1 modi?cations: ? added t ab le 11 dynamic char acter istics: static e xter nal memor y interf ace . ? added t ab le 12 dynamic char acter istics: dynamic e xter nal memor y interf ace . ? added figure 9 exter nal memor y read access . ? added figure 10 exter nal memor y wr ite access . ? t ab le 7 , v hys , moved 0.4 from typ to min column. ? t ab le 7 , added t ab le note 6 . lpc2458_1 20080623 product data sheet - -
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 65 of 67 nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. softconnect is a trademark of nxp b.v. goodlink is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
lpc2458_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 25 november 2008 66 of 67 continued >> nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 20 7.1 architectural overview. . . . . . . . . . . . . . . . . . . 20 7.2 on-chip ?ash programming memory . . . . . . . 21 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 23 7.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24 7.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 24 7.7 external memory controller. . . . . . . . . . . . . . . 24 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.8 general purpose dma controller . . . . . . . . . . 25 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.9 fast general purpose parallel i/o . . . . . . . . . . 26 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.10 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.11 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.11.1 usb device controller . . . . . . . . . . . . . . . . . . . 28 7.11.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.11.2 usb host controller . . . . . . . . . . . . . . . . . . . . 28 7.11.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.11.3 usb otg controller . . . . . . . . . . . . . . . . . . . . 29 7.11.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12 can controller and acceptance ?lters . . . . . . 29 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.13 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.15 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.16 spi serial i/o controller. . . . . . . . . . . . . . . . . . 31 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.17 ssp serial i/o controller . . . . . . . . . . . . . . . . . 31 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.18 sd/mmc card interface . . . . . . . . . . . . . . . . . 31 7.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.19 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 32 7.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.20 i 2 s-bus serial i/o controllers . . . . . . . . . . . . . 32 7.20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.21 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 33 7.21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.22 pulse width modulator . . . . . . . . . . . . . . . . . . 34 7.22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.23 watchdog timer (wdt). . . . . . . . . . . . . . . . . . 35 7.23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.24 rtc and battery ram . . . . . . . . . . . . . . . . . . 35 7.24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.25 clocking and power control . . . . . . . . . . . . . . 36 7.25.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 36 7.25.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 36 7.25.1.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 36 7.25.1.3 rtc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 37 7.25.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.25.3 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 37 7.25.4 power control . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.25.4.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.25.4.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.25.4.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 38 7.25.4.4 power domains. . . . . . . . . . . . . . . . . . . . . . . . 39 7.26 system control . . . . . . . . . . . . . . . . . . . . . . . . 39 7.26.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.26.2 brownout detection . . . . . . . . . . . . . . . . . . . . 40 7.26.3 code security (code read protection - crp) 40 7.26.4 ahb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.26.5 external interrupt inputs . . . . . . . . . . . . . . . . . 41 7.26.6 memory mapping control . . . . . . . . . . . . . . . . 41 7.27 emulation and debugging. . . . . . . . . . . . . . . . 41 7.27.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 41 7.27.2 embedded trace. . . . . . . . . . . . . . . . . . . . . . . 41 7.27.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 43 9 static characteristics . . . . . . . . . . . . . . . . . . . 44 10 dynamic characteristics . . . . . . . . . . . . . . . . . 50 10.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11 application information . . . . . . . . . . . . . . . . . 56 11.1 suggested usb interface solutions . . . . . . . . 56 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 62 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 63 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 64 15 legal information . . . . . . . . . . . . . . . . . . . . . . 65 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 65
nxp semiconductors lpc2458 single-chip 16-bit/32-bit microcontroller ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 25 november 2008 document identifier: lpc2458_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16 contact information. . . . . . . . . . . . . . . . . . . . . 65 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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